This invention relates to data communications in a computer system, and more particularly to a memory controller operable to issue variable length read and write commands.
Modern computer systems typically include a host processor coupled to a host bridge. The host bridge interfaces the processor to the rest of the computer system. The host bridge may include a memory controller that is coupled to a system memory, for example Dynamic Random Access Memory (DRAM). A single memory controller can support a plurality of memory channels, where each memory channel is an electrically independent interface with the memory channel""s own data bus connecting the memory channel to the memory controller. The larger the number of memory channels, the larger the aggregate bandwidth (amount of information transferred per second between the DRAM and the memory controller). Increasing the number of memory channels also increases the aggregate storage capacity of the memory subsystem by allowing more memory modules/devices to be connected to a single controller.
Most memory controllers perform read and write commands in fixed size amounts of data. This amount of data is called a xe2x80x9clinexe2x80x9d. A line contains L bytes of data. For example, when the memory controller performs a read operation, the controller receives a single line of data (L bytes) for each read command issued. Likewise, when the memory controller performs a write operation, the memory controller transmits a line of data (L bytes) for each write command issued. In an n-channel implementation, each of the channels returns a line of data for each read command. The total amount of data returned to the controller is L*n bytes if all channels are populated. For write commands, the controller transmits L*n bytes, with L bytes being written to each usable memory channel.
Referring to FIG. 1, timing diagram 100 illustrates the operation of a memory controller supporting two channels 101 and 102 with a fixed burst length L=4. As shown, only channel 101 is populated. Assuming a requesting agent requests R=8 bytes of data 104A-H, the controller would be required to issue two read commands 105A and 105B. The first read command 105A would issue at the rising edge of clock 0106, and the second read command 105B would issue at the rising edge of clock 4107. In contrast, assuming both channels are populated and the controller uses multiple channels in a lock-step fashionxe2x80x94i.e., each channel receives the same read and write commands and the data is split between the channelsxe2x80x94the controller would only be required to issue one read command of length L=4. The single read command would enable the controller to receive the full L*n or 8 bytes. By requiring a larger number of read or write commands in the event that all channels are not populated, conventional memory controllers suffer performance and efficiency losses.